Fusion Semiconductor

07/08/2026

Hiring: PCM Layout Engineer (Process Control Monitor) – SKILL Scripting

01/08/2026

We are honored to collaborate with the Collaborative Microelectronic Design Excellence Centre (CEDEC) at Universiti Sains Malaysia (USM), one of Malaysia's leading public universities, and to have been invited for the third time to serve as a trainer for the Professional Training Program in Integrated Circuit (IC) Design. This opportunity reflects a shared commitment to developing Malaysia's next generation of IC design professionals.

14/07/2026

We’re Hiring: 10+ Analog Mixed-Signal Layout Engineers

Join our growing team in Penang, Malaysia!

We are expanding our Offshore Development Center (ODC) projects and are looking for 10+ experienced Analog Mixed-Signal Layout Engineers to join us.

Requirements:

* 3+ to 10 years of experience in Analog/Mixed-Signal IC Layout
* Hands-on experience with 7nm and below technology nodes
* Experience in one or more of the following IPs:
* SerDes (RX, TX, CDR, CTLE, DFE, PLL, Clocking, or other SerDes building blocks)
* LDO
* IO/ESD

Location:
📍 Penang, Malaysia

What You’ll Work On:

* Cutting-edge AMS/RF IC layout projects for advanced semiconductor products
* Collaboration with experienced global engineering teams
* Advanced technology nodes and challenging SoC designs

How to Apply:
Please send your resume to:
📧 [email protected] or [email protected]

Subject: Application for AMS Layout Engineer Position

We welcome passionate engineers who are eager to work on advanced semiconductor technologies and grow their careers with us.

Thank you!

26/05/2026

📢 Job Opportunities – Analog Layout Design Engineers (Multiple Positions)

Hi All,

We are hiring Analog Layout Design Engineers with 4+ years of experience in advanced FinFET technologies for our client, AMD Malaysia.

🔍 Required Experience:

* Strong hands-on expertise in Analog & Mixed-Signal Layout Design
* Experience working on advanced FinFET nodes
* SerDes block layout experience is highly preferred
* Solid understanding of physical verification, matching, parasitics, and layout best practices
* Candidates should be willing to relocate to Penang, Malaysia

If you are interested, please send your updated CV, including your Analog Layout project experience, to:

📧 [email protected]

Please feel free to share this opportunity within your network.

Thank you!

04/04/2026

Job Openings: SRAM Memory Layout Engineer & Physical Design Engineer

We are currently hiring multiple SRAM Memory Layout Engineers and Physical Design Engineers to join our team in Malaysia.

Requirements:

For SRAM Memory Layout Engineer:
• 4 to 8 years of hands-on experience in SRAM memory layout design
• Strong expertise in advanced FinFET technology nodes
• Proven experience in full custom layout for SRAM bitcells and related blocks

For Physical Design Engineer:
• 4 to 8 years of experience in Physical Design (RTL-to-GDSII)
• Strong knowledge of advanced FinFET technology nodes
• Experience in floorplanning, placement, CTS, routing, and physical verification flows
• Familiarity with industry-standard EDA tools and methodologies

Location:

Onsite role in Malaysia

Interested candidates are invited to send their CVs with the subject line:
• “SRAM Memory Layout Engineer” or
• “Physical Design Engineer”

Please include detailed project experience and send to:
[email protected]

19/03/2026

02/03/2026

We are truly honored to contribute to the development of Malaysia’s future engineers through training, mentorship, and the sharing of our industry expertise.

18/02/2026

Ramadan Kareem!

10/02/2026

We have just started our three-month custom IC layout design training program in collaboration with Prime Silicon Technology, Bangladesh. Upon successful completion of the training, most trainees are expected to secure employment at Prime Silicon Technology.

Best wishes to all the trainees for a successful learning journey.

13/01/2026

We will be conducting a 3-month Basic to Advanced IC Layout Design training program for an established company in Bangladesh.

Candidates interested in a 3-month internship or trainee engineer position are invited to submit their CV to [email protected] by tomorrow, 14 January 2026.

Minimum Requirements:
• Already graduated
• Completed coursework in VLSI and Electronics

Additional Preference:
• Priority will be given to candidates with hands-on experience in Cadence Virtuoso

There are three additional internship slots available in this training program. Only shortlisted candidates will be contacted.

Thank you!