Ulkasemi

18/06/2026

𝐔𝐋𝐊𝐀 𝐁𝐈𝐓𝐒-𝟏𝟑

𝐀 𝐬𝐢𝐧𝐠𝐥𝐞 𝐯𝐨𝐥𝐭𝐚𝐠𝐞. 𝐀 𝐛𝐢𝐠 𝐝𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐜𝐞.

In digital design, a signal is not considered a valid logic ‘1’ just because it looks high. The input voltage must satisfy a specific condition before the circuit recognizes it as a logic HIGH.

𝐃𝐫𝐨𝐩 𝐲𝐨𝐮𝐫 𝐚𝐧𝐬𝐰𝐞𝐫 𝐛𝐞𝐥𝐨𝐰 and 𝐭𝐚𝐠 𝐭𝐡𝐚𝐭 𝐟𝐫𝐢𝐞𝐧𝐝 who always claims Digital Electronics was easy.

15/06/2026

ULKASEMI was honored to engage in a fruitful discussion with 𝐇𝐨𝐧𝐨𝐫𝐚𝐛𝐥𝐞 𝐌𝐢𝐧𝐢𝐬𝐭𝐞𝐫 𝐅𝐚𝐪𝐢𝐫 𝐌𝐚𝐡𝐛𝐮𝐛 𝐀𝐧𝐚𝐦, 𝐌𝐢𝐧𝐢𝐬𝐭𝐫𝐲 𝐨𝐟 𝐏𝐨𝐬𝐭𝐬, 𝐓𝐞𝐥𝐞𝐜𝐨𝐦𝐦𝐮𝐧𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐚𝐧𝐝 𝐈𝐧𝐟𝐨𝐫𝐦𝐚𝐭𝐢𝐨𝐧 𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐲, and 𝐌𝐫. 𝐀𝐧𝐰𝐚𝐫 𝐇𝐨𝐬𝐬𝐚𝐢𝐧, 𝐀𝐝𝐦𝐢𝐧𝐢𝐬𝐭𝐫𝐚𝐭𝐨𝐫 𝐨𝐟 𝐁𝐆𝐌𝐄𝐀.

The meeting reflected the importance of cross-sector dialogue and collaboration in shaping Bangladesh's future. We are grateful for the opportunity to exchange ideas and perspectives, and remain committed to contributing to the country's journey toward technological advancement and sustainable growth.

11/06/2026

𝐔𝐋𝐊𝐀 𝐁𝐈𝐓𝐒 - 𝟏𝟐

A quick challenge for the future chip designers and semiconductor enthusiasts out there. Can you identify the correct relationship? Share your answer in the comments below.

𝐁𝐞𝐜𝐚𝐮𝐬𝐞 𝐠𝐫𝐞𝐚𝐭 𝐞𝐧𝐠𝐢𝐧𝐞𝐞𝐫𝐬 𝐝𝐨𝐧'𝐭 𝐣𝐮𝐬𝐭 𝐦𝐞𝐦𝐨𝐫𝐢𝐬𝐞 𝐞𝐪𝐮𝐚𝐭𝐢𝐨𝐧𝐬, 𝐭𝐡𝐞𝐲 𝐮𝐧𝐝𝐞𝐫𝐬𝐭𝐚𝐧𝐝 𝐭𝐡𝐞 𝐩𝐫𝐢𝐧𝐜𝐢𝐩𝐥𝐞𝐬 𝐛𝐞𝐡𝐢𝐧𝐝 𝐭𝐡𝐞𝐦.

11/06/2026

𝐀𝐫𝐞 𝐰𝐞 𝐫𝐞𝐚𝐝𝐲 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐜𝐡𝐢𝐩 𝐞𝐫𝐚?

In a recent op-ed published in The Daily Star, our 𝐂𝐄𝐎 & 𝐏𝐫𝐞𝐬𝐢𝐝𝐞𝐧𝐭 𝐌𝐨𝐡𝐚𝐦𝐦𝐞𝐝 𝐄𝐧𝐚𝐲𝐞𝐭𝐮𝐫 𝐑𝐚𝐡𝐦𝐚𝐧 explores how Bangladesh can position itself in the rapidly evolving global semiconductor landscape.

With the semiconductor industry projected to 𝐬𝐮𝐫𝐩𝐚𝐬𝐬 $𝟏 𝐭𝐫𝐢𝐥𝐥𝐢𝐨𝐧 𝐛𝐲 𝟐𝟎𝟑𝟎, the demand for skilled talent is growing faster than ever. Bangladesh has the potential to contribute meaningfully to this transformation, but unlocking that potential will require strategic investment in skills development, stronger industry-academia collaboration, and long-term national commitment.

𝐑𝐞𝐚𝐝 𝐭𝐡𝐞 𝐟𝐮𝐥𝐥 𝐚𝐫𝐭𝐢𝐜𝐥𝐞 𝐡𝐞𝐫𝐞: https://www.thedailystar.net/business/column/news/are-we-ready-the-chip-era-4195676

Bangladesh is at a moment of silent but significant transformation. One driven by technology, skills development and industrial diversification amid economic pressures and global uncertainty. This is the time to think clearly and plan ahead.

10/06/2026

𝐓𝐡𝐞 𝐰𝐨𝐫𝐥𝐝 𝐢𝐬 𝐚𝐝𝐯𝐚𝐧𝐜𝐢𝐧𝐠 𝐭𝐡𝐫𝐨𝐮𝐠𝐡 𝐜𝐡𝐢𝐩𝐬. 𝐀𝐫𝐞 𝐰𝐞 𝐫𝐞𝐚𝐝𝐲?

In a recently published news, 𝐨𝐮𝐫 𝐂𝐄𝐎, 𝐌𝐨𝐡𝐚𝐦𝐦𝐞𝐝 𝐄𝐧𝐚𝐲𝐞𝐭𝐮𝐫 𝐑𝐚𝐡𝐦𝐚𝐧, explores the opportunities and challenges that lie ahead for Bangladesh in the global semiconductor landscape.

From addressing 𝐭𝐡𝐞 𝐠𝐫𝐨𝐰𝐢𝐧𝐠 𝐭𝐚𝐥𝐞𝐧𝐭 𝐠𝐚𝐩 𝐚𝐧𝐝 𝐬𝐭𝐫𝐞𝐧𝐠𝐭𝐡𝐞𝐧𝐢𝐧𝐠 𝐢𝐧𝐝𝐮𝐬𝐭𝐫𝐲-𝐚𝐜𝐚𝐝𝐞𝐦𝐢𝐚 𝐜𝐨𝐥𝐥𝐚𝐛𝐨𝐫𝐚𝐭𝐢𝐨𝐧 to 𝐜𝐫𝐞𝐚𝐭𝐢𝐧𝐠 𝐩𝐨𝐥𝐢𝐜𝐲 𝐬𝐮𝐩𝐩𝐨𝐫𝐭 𝐚𝐧𝐝 𝐚𝐭𝐭𝐫𝐚𝐜𝐭𝐢𝐧𝐠 𝐟𝐨𝐫𝐞𝐢𝐠𝐧 𝐢𝐧𝐯𝐞𝐬𝐭𝐦𝐞𝐧𝐭, the article highlights what it will take for Bangladesh to move from being a technology consumer to becoming a technology creator.

𝐑𝐞𝐚𝐝 𝐭𝐡𝐞 𝐟𝐮𝐥𝐥 𝐚𝐫𝐭𝐢𝐜𝐥𝐞 𝐡𝐞𝐫𝐞: https://www.jugantor.com/tp-ub-editorial/1111144

এক গুরুত্বপূর্ণ সন্ধিক্ষণে দাঁড়িয়ে আছে বাংলাদেশ। খুব নিঃশব্দে একটা বড় পরিবর্তন ঘটছে; শুধু বাংলাদেশে নয়, বিশ্বজু....

25/05/2026

May this 𝐄𝐢𝐝 𝐚𝐥-𝐀𝐝𝐡𝐚 fill your home with happiness, your heart with peace, and your days with countless blessings.

Wishing you and your loved ones a joyful and memorable Eid.

𝐄𝐢𝐝 𝐌𝐮𝐛𝐚𝐫𝐚𝐤 𝐟𝐫𝐨𝐦 𝐔𝐋𝐊𝐀𝐒𝐄𝐌𝐈.

22/05/2026

WE ARE HIRING!

ULKASEMI started its journey in 2007 in Silicon Valley, USA and Gradually it expanded its operation in Canada, India and Bangladesh. Since its inception ULKASEMI has been playing the pioneer role in the semiconductor design service industry.

Position Name : Principal Engineer
Department Name : Layout
Job Type : Full-time
Job Location : Penang, Malaysia

Job Overview:
As a Principal Layout Engineer, you are an acknowledged specialist at ADI, tackling particularly important and intricate layout problems that are strategically critical to the company.

Job Responsibilities:
1. Lead the physical design and layout implementation of high-performance analog, mixed-signal, RF, and digital products and subsystems, including ADCs, DACs, PLLs, SERDES, transceivers, and high-speed interfaces.

2. Design, integrate, and optimize complex chips and subsystems using advanced CMOS FinFET technologies (16nm and below).

3. Develop and manage floorplanning strategies at the block, subsystem, and full-chip levels for large-scale and high-complexity designs.

4. Collaborate closely with cross-functional teams—including analog design, RTL, DFT, timing, clocking, power integrity, packaging, and verification teams—to ensure smooth integration and successful tape-out ex*****on.

5. Drive and continuously improve physical design methodologies, layout automation flows, and best practices to enhance design quality, productivity, and scalability.

6. Lead physical verification activities including DRC, LVS, ERC, antenna checks, density verification, parasitic extraction, EM/IR analysis, reliability verification, and tape-out signoff.

7. Analyze and resolve complex layout, signal integrity, reliability, matching, and manufacturability challenges.

8. Create project schedules, track ex*****on progress, manage technical risks, and ensure timely delivery of high-quality design milestones.

9. Mentor and technically guide layout engineers and cross-functional team members, fostering engineering excellence and knowledge sharing.

10. Support recruitment, technical evaluation, and capability development initiatives within the organization.

11. Contribute to strategic technology planning, process improvement initiatives, and organizational technical roadmap development.

Preferred Education and Experience:
1. Bachelor's degree in engineering, Electronics, Electrical Engineering, Microelectronics, or related field

2. MSc/MEng/M.Tech preferred

3. 12+ years of relevant experience in semiconductor physical design and IC layout engineering

Required Tool Expertise

IC Layout Software: Cadence Virtuoso, Synopsys Custom Compiler.
Verification Engines: Siemens Calibre, Synopsys IC Validator.
Scripting Languages: Skill, Perl, Python, or Tcl for workflow automation.

Application Deadline: 05 Jun 2026
Application Link: https://forms.gle/B7dZCMeKJCYrYboYA

22/05/2026

WE ARE HIRING!

ULKASEMI started its journey in 2007 in Silicon Valley, USA and Gradually it expanded its operation in Canada, India and Bangladesh. Since its inception ULKASEMI has been playing the pioneer role in the semiconductor design service industry.

Position Name : Principal Engineer
Department Name : IC Physical Design (PnR)
Job Type : Full-time
Job Location : Penang, Malaysia

Job Overview:
The Principal Engineer – Physical Design (PnR) is a senior technical leadership position tasked with overseeing the complete physical implementation of sophisticated ASIC/SoC designs. The position guarantees optimal PPA (Power, Performance, Area), readiness for high-quality tape-out, and provides technical guidance for the PnR team in Penang.

Job Responsibilities:
1. Lead end-to-end physical design implementation for complex SoC/sub-system/IPs/blocks from RTL to GDS on cutting-edge technology nodes.
2. Drive floor planning, power planning, placement, CTS, routing, optimization, and low-power design implementation.
3. Handle timing, congestion, IR drop, EM, noise, and physical verification closure, including final signoff approval.
4. Analyze and resolve design bottlenecks to achieve PPA targets.
5. Establish and improve optimal methodologies, techniques, and design approaches for the PnR process.
6. Work closely with cross-functional teams to deliver high-quality outcomes.
7. Mentor junior and mid-level engineers and contribute to overall team development.
8. Support tape-out activities and participate in customer technical discussions.
9. Assist with tape-out ex*****on and post-silicon debugging/troubleshooting activities.
10. Collaborate closely with global teams across multiple sites.

Qualifications:
1. Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.
2. 10+ years of hands-on experience in IC Physical Design in advanced process nodes (16nm/7nm/5nm/2nm or below preferred).
3. Proficiency in industry-standard EDA tools and techniques for physical design implementation and verification.
4. Experience in optimizing designs for power, performance, and area (PPA) targets.
5. Strong understanding of low-power design techniques.
6. Ability to analyze and resolve complex design challenges through disciplined ex*****on.
7. Experience leading teams or owning major project deliverables.
8. High degree of initiative enthusiasm and out-of-the-box thinking capabilities.

Application Deadline: 05 June 2026
Application Link: https://forms.gle/cPW6MNGmdsLr45pn8

22/05/2026

The 𝐔𝐋𝐊𝐀𝐒𝐄𝐌𝐈 𝟗-𝐃𝐚𝐲 𝐈𝐧𝐝𝐮𝐬𝐭𝐫𝐢𝐚𝐥 𝐓𝐫𝐚𝐢𝐧𝐢𝐧𝐠 𝐏𝐫𝐨𝐠𝐫𝐚𝐦 concluded with a certificate awarding ceremony, celebrating the successful participation of 𝐨𝐯𝐞𝐫 𝟗𝟎 𝐬𝐭𝐮𝐝𝐞𝐧𝐭𝐬 from 𝟏𝟎 𝐮𝐧𝐢𝐯𝐞𝐫𝐬𝐢𝐭𝐢𝐞𝐬.

Throughout the program, participants explored key areas of the semiconductor industry while gaining practical insights from experienced professionals and industry experts.

𝐀 𝐬𝐩𝐞𝐜𝐢𝐚𝐥 𝐭𝐡𝐚𝐧𝐤 𝐲𝐨𝐮 to all our trainers who dedicated their time, knowledge, and mentorship to help inspire the next generation of semiconductor engineers.

21/05/2026

WE ARE HIRING!

ULKASEMI started its journey in 2007 in Silicon Valley, USA and Gradually it expanded its operation in Canada, India and Bangladesh.

Position Name : Engineer/Senior Engineer
Department Name : Layout
Job Type : Full-time
Job Location : Penang, Malaysia

Job Overview:
We are looking for talented individuals to join the Design Engineering team as a Layout Design Engineer/Senior Engineer in advanced process technology node. As a full-time Engineer/Senior Engineer, He/she will be responsible for implementing floor planning, designing standard and custom analog and digital layouts.

Job Responsibilities:

Engineer:

1. Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience
2. Experience in the layout of Memory, high performance data converters and / or high speed (GHz) circuit design would be an advantage
3. Extensive Floor planning, power grid and signal flow planning experience
4. Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
5. Excellent understanding of signal and clock shielding and isolation techniques
6. Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects
7. Excellent written and oral communication skills are also required

Senior Engineer:

1. Extensive section (multi-hierarchical) level layout experience
2. Experience with Floor-planning large Blocks
3. High proficiency in interpretation of LVS/DRC/ERC/ANTENNA/DENSITY/DFM
4. Expertise in standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well’s substrates and Isolation.
5. Experience in laying out circuits for ESD consideration
6. Strong fundamental knowledge in semiconductor device physics, cross-section and construction
7. Strong fundamental knowledge in layout principles, IC reliability and failure mechanisms
8. Excellent written and oral communication skills are also required
9. Ability to work well as part of a team

Preferred Education and Experience:
1. Bachelor’s degree in Engineering, Electronics, Electrical Engineering, Microelectronics, or related field
2. MSc/MEng/M.Tech preferred
3. 4+ years of relevant experience

Other Requirements:
1. Strong understanding of CMOS circuit fundamentals and semiconductor device behavior.
2. Ability to communicate effectively with cross-functional engineering teams regarding layout requirements and design constraints.
3. Strong analytical, problem-solving, and debugging skills.
4. Good written and verbal communication skills.
5. Ability to work effectively in a collaborative team environment.
6. Self-motivated, detail-oriented, and eager to learn advanced semiconductor technologies.

Application Deadline: 05 June 2026
Application Link: https://forms.gle/1okSnJFJYuEdvyaQ9