Marvell Technology

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Data Center & Cloud | Carrier | Enterprise We believe that infrastructure powers progress. At Marvell, We go all in with you.

That ex*****on is as essential as innovation. That better collaboration builds better technology. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for une

xpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

As AI clusters scale and Mixture of Experts architectures grow in complexity, the diversity of interconnect standards is...
06/22/2026

As AI clusters scale and Mixture of Experts architectures grow in complexity, the diversity of interconnect standards is expanding rapidly. UALink, ESUN, NVLink, and others are creating what Preet Virk calls a "chiplet smorgasbord," a proliferation of die-to-die interfaces, protocols, physical layers, and external interfaces that demands a fundamentally different design approach.

Preet will deliver a keynote at the EE Times Chiplet Summit exploring how system-level co-design across compute, switches, and memory, anchored by architectural control of SerDes, optics, advanced packaging, and test IP, is essential to managing this complexity at scale.

Register for this virtual event here: https://mrvl.co/4uLxLqb

SerDes is the foundational building block of high-speed networking, present in every XPU, switch, high-speed interface, ...
06/18/2026

SerDes is the foundational building block of high-speed networking, present in every XPU, switch, high-speed interface, and optical component in a modern data center. Its performance has a direct impact on power consumption, latency, bandwidth, link length, and ultimately total cost of ownership.

Marvell has doubled the line speed of its leading SerDes approximately every two years. The most recent demonstration of 224G long-range SerDes achieved lane bit error rates of 1e-11 at 4 picojoules per bit across a 2.5-meter CPC-backplane-CPC channel, with up to 512 lanes integrable into a 102.4T switch.

Senior Staff Engineer Aatreya Chakravarti explains how the technology works, where it fits within the broader connectivity stack, and why SerDes leadership remains central to scaling AI infrastructure: https://mrvl.co/44fVLXD

Contemporary silicon photonics modulators are constrained by the diffraction limit of light, restricting their ability t...
06/17/2026

Contemporary silicon photonics modulators are constrained by the diffraction limit of light, restricting their ability to scale efficiently to the bandwidths AI infrastructure will require. Plasmonics offers a path forward.

By compressing light below the diffraction limit at a metal-dielectric interface, plasmonic modulators can operate at speeds exceeding 1 THz, more than 10x faster than conventional photonic modulators, while measuring approximately 10 microns in length, 300x to 500x shorter. The result is exponentially higher bandwidth density within the same silicon photonics platform, without requiring a shift to new material systems.

Marvell Senior Director Claudia Hoessbacher and Director Wolfgang Heni of Optical Engineering detail the technology, its applications across scale-up and scale-across networks, and where development stands today.

Read more: https://mrvl.co/4a8nRaK

Deploying next-generation optical connectivity at the pace AI infrastructure demands requires more than advanced technol...
06/16/2026

Deploying next-generation optical connectivity at the pace AI infrastructure demands requires more than advanced technology. It requires standards that reduce integration complexity and give data center operators flexibility at the time of deployment.

The Open CPX MSA, which includes Marvell among its members, is building that foundation. A single CPX array can be configured to support co-packaged copper for intra-rack connections, co-packaged optics for rack-to-rack communication, and ZR/ZR+ modules for long-distance interconnects, with port configurations determined at deployment rather than at design time.

With near- and co-packaged port shipments projected to grow from under one million in 2025 to more than 100 million per year by 2030, that kind of flexibility matters. George Hervey explains what Open CPX makes possible: https://mrvl.co/4emX2Ro

In an exclusive interview with DIGITIMES at Computex 2026, Marvell President and Chief Operating Officer Chris Koopmans ...
06/15/2026

In an exclusive interview with DIGITIMES at Computex 2026, Marvell President and Chief Operating Officer Chris Koopmans covered a lot of ground: the company's decade-long transformation into a data infrastructure leader, why securing supply chain capacity is ultimately about trust, and how the transition from copper to optical will unfold over the next five years in scale-up networks.

On the copper wall: "The copper wall will eventually fall." On the ASIC business: it is fundamentally an I/O business, not an XPU business. And on supply constraints: the current environment may actually be healthier for the long-term trajectory of the AI industry than unconstrained growth would be.

A substantive read for anyone tracking where AI infrastructure is headed: https://mrvl.co/4eKstGA

One of AI's three big problems is power consumption, which is becoming a hard constraint in AI infrastructure. Data cent...
06/10/2026

One of AI's three big problems is power consumption, which is becoming a hard constraint in AI infrastructure. Data center power limits are tightening, and a significant portion of the energy modern AI systems consume is spent simply moving data between compute and memory.

Marvell Photonic Fabric technology addresses that directly. By integrating optics closer to the XPU, the platform delivers up to 2x greater energy efficiency compared to copper, while also supporting up to 2x more compute within the same power and space footprint.

The same platform extends scale-up clusters beyond a single rack, and enables pod-scale memory sharing across systems. Senior Director of Product Management Uday Poosarla details how it all works together: https://mrvl.co/4g8fq2P

06/09/2026

Memory architecture is a technical challenge, but it is also a financial one. This clip puts the economics in clear terms.

At the International Semiconductor Industry Group (ISIG) Executive Summit, Sandeep Bharathi makes the capital allocation case for memory pooling. When processors cannot access their full dedicated memory, the unused capacity is stranded, generating cost without generating value. Pooling that memory across systems can reduce total cost of ownership by 50 to 70%.

The business model implications follow directly: lower TCO, faster time to first token, and higher throughput per millisecond translate to better margins for hyperscalers running inference at scale.

06/08/2026

A powerful week at COMPUTEX 2026. Marvell brought forward breakthrough innovation and a compelling vision for the evolution of AI infrastructure. The energy was electric and the momentum across the ecosystem is unmistakable.

Learn more: mrvl.co/4dCO6s7

For the 13th year, Marvell employees laced up and ran together, spanning 36 sites across the globe.The Marvell Global 5K...
06/05/2026

For the 13th year, Marvell employees laced up and ran together, spanning 36 sites across the globe.

The Marvell Global 5K has become more than an annual event. It reflects something true about how this company operates: the work is demanding, the problems we solve are consequential, and we do it as one team, no matter the time zone.

Building the semiconductor infrastructure that powers AI takes endurance, precision, and the kind of collaboration that only comes from a team that genuinely enjoys working together. The Global 5K is a reminder of all three.
Congratulations to every runner, volunteer, and organizer who made this year's event possible across six continents.

06/04/2026

The tension between memory access and compute performance is not a new problem. What is new is the scale at which AI infrastructure has made it urgent.

In this clip from the International Semiconductor Industry Group (ISIG) Executive Summit, Marvell President of the Data Center Group Sandeep Bharathi traces the memory hierarchy challenge from early CPU design through to modern AI inference, and explains why re-architecting memory at the system level has become a foundational requirement. He also introduces CXL as one of the key techniques for bringing memory closer to compute, using a return to his restaurant analogy to illustrate why consistency and accessibility are equally critical.

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